1. Field of the Invention
The present invention relates to a system, method, and program for returning data to read requests received over a bus.
2. Description of the Related Art
FIG. 1 illustrates a prior art storage device architecture, where an external bus master 2, such as a network adaptor (e.g., a Fibre Channel controller, Ethernet controller, etc.) may access data in one or more disks 4, 6 through a Serial Advanced Technology Attachment (SATA) controller 8 over a Peripheral Component Interconnect (PCI) bus 10, which may utilize the Peripheral Component Interconnect (PCI) or PCI-X protocol. In prior art systems, data being transferred between the external bus master 2 and SATA controller 8 first typically flows through a memory controller 12 and memory 14, such as a Static Dynamic Random Access Memory (SDRAM). For instance, when the external bus master 2 wants to write data to the disks 4, 6, the external bus master 2 may transfer the data to the memory 14. The SATA controller 8 may then read the data sent to the memory 14 in the write request and write the data to disk 4, 6. For a read operation, the SATA controller 8 typically transfers requested read data to the memory 14 and the external bus master 2 typically accesses the read data from the memory 14. The controllers 2 and 8 may include Direct Memory Access (DMA) engines that perform the actual data movement operations therebetween through the memory 14.
Further, in the PCI-X prior art, the memory buffer 14 enables read and write bursts between an external bus master 2 and a SATA controller 8, because current SATA controllers must operate as a bus master to handle burst data transfers. Further details of the PCI and PCI-X protocol are described in the publications xe2x80x9cPCI Local Bus Specificationxe2x80x9d, Rev. 2.3 (PCI Special Interest Group, March 2002) and xe2x80x9cPCI-X Addendum to the PCI Local Bus Specificationxe2x80x9d, Rev. 1.0a (PCI Special Interest Group, July 2000).
Using the memory 14 component to buffer data being transferred between the controllers 2 and 8 provides additional latency and delays because of the additional read and write operations involved in using the memory 14 as an intermediary buffer. For these reasons, there is a need in the art for improved techniques for transferring data between controllers in a bus architecture.